A finished IT 105 Unit 3 instruction cycle trace: starting state fixed, one row per phase, each transfer named, and the program counter accounted for throughout. Searches like "it 105 unit 3 assignment example", "it105 unit 3 sample" and "it 105 unit 3 example" land here.
What a finished IT 105 Unit 3 instruction cycle trace looks like
The centerpiece is a table and the prose around it is thin by design. Above the table, a short block declares the model being traced: which registers exist, how wide they are, what the instruction format looks like, and what is sitting in memory and in each register before the cycle starts. The table then runs one row per phase, with columns for the phase name, the transfer that occurs written in the course's register transfer notation, the contents of each register after that phase, and a plain clause saying why the transfer is needed. Fetch, decode and execute each occupy their own rows, subdivided where the section's model subdivides them. A closing comparison sets the ending state beside the starting state and names every register that changed, including the ones that changed as bookkeeping.
How a IT 105 Unit 3 example is structured
The model is declared first because a trace is only meaningful against a stated machine, and two students tracing the same instruction on different assumed designs will legitimately produce different tables. State is shown after each phase rather than only at the end, since the point of the exercise is the progression and a single final snapshot hides where an error entered. Transfers are written in notation rather than described in a sentence, as the notation forces a claim about exactly what moved into exactly what and prose allows a writer to be vague. The reason column sits beside the transfer so the trace reads as design logic rather than as ritual. Program counter behavior gets explicit treatment in every row because it is the detail drafts most often strand somewhere between fetch and execute. The closing comparison catches changes nobody intended.
The assumed machine declared first
Registers, widths, instruction format and the starting contents of memory are stated before the trace, since the table means nothing otherwise.
One row for each phase
Fetch, decode and execute each occupy their own row, subdivided wherever the model your own section teaches happens to subdivide them further.
Transfers written in notation
Each row records what moved into what using register transfer notation, which forces precision that a prose description quietly allows you to avoid.
Register contents after every phase
The state is snapshotted repeatedly rather than once at the end, because a single closing picture conceals where an error first appeared.
The program counter accounted for throughout
Every row says what the counter holds, since its increment is the detail most drafts leave stranded somewhere in the middle.
Ending state compared to the start
A closing block names each register that changed across the cycle, which exposes any value that moved without an instruction moving it.
Where marks go in IT 105 Unit 3
Traces lose credit when they narrate. A paragraph reciting that the processor fetches, then decodes, then executes repeats the textbook and shows no machine doing anything. Tables with no starting state leave every row unverifiable, since nothing can be checked against what was there before. A program counter that appears in the first row and vanishes afterward leaves the next fetch unexplained. Decode rows that already perform the operation have collapsed two phases and lost the distinction the unit exists to teach. Values appearing in a register that no listed transfer wrote to are the clearest sign a table was filled in from the expected answer. Instruction encodings invented without declaring the format assumed cannot be decoded by a reader at all.
Get a IT 105 Unit 3 example written to your instructions
Post us the unit instructions, your IT 105 rubric, and whichever machine model, register set or notation your section uses for tracing. The custom example declares the assumed design, gives each phase a row, writes transfers in notation, snapshots the registers repeatedly, tracks the counter throughout and compares the closing state. First custom sample free, 24-48h.
IT 105 Unit 3 questions, answered
Which instruction should the trace follow?
Take the one the assignment names, and where the choice is open, prefer an instruction that touches memory as well as registers because it exercises more phases and gives the table something to show. A register to register operation traces quickly and leaves several criteria with nothing to grade. Avoid anything so unusual that the format itself needs a page of explanation first.
Does the trace need a real instruction set?
It needs a declared one, which is not the same thing. Many sections teach a simplified teaching machine precisely so the cycle stays visible, and a trace against that model is entirely correct. If you use a documented commercial set, cite the reference you read and hold to it, because half remembered details from one design mixed into another make the whole table arguable.
How detailed should the phase breakdown be?
Match the model your classroom teaches rather than the most elaborate version available. If the section splits execute into separate memory and write back steps, split them; if it does not, adding stages invents a machine the rubric was not written against. The safest test is whether every row corresponds to something the course's own diagram shows.